The present invention relates generally to electrical circuits, and more particularly to a system and method for reducing timing mismatch in sample and hold circuits.
Analog to digital converters (ADCs) are important analog circuit devices which take an analog input signal and generate one or more digital signals which are representative of the analog input. ADCs are used in many applications such as communications applications in which the components receive a voice input (an analog input) and transform the voice date into a digital format for internal processing. Exemplary applications using such ADCs are illustrated in prior art FIGS. 1 and 2, respectively. For example, in prior art FIG. 1, an exemplary base transceiver station (BTS) 10 is illustrated in which an RF analog input signal 12 is received, amplified and converted into a digital signal 14 before being processed in a baseband section 16 and network interface section 18. Similarly, prior art FIG. 2 illustrates a schematic diagram of an automobile multimedia system 20 in which various analog signals such as radio signals 22 and sensor signals 24 are transformed into digital signals for subsequent processing. Further, many other system applications exist, including, but not limited to, hard disk drive (HDD) read channel applications.
One of the most challenging portions of an ADC is the sample and hold (S/H) circuit at the front end thereof. As the speed of ADCs continues to grow, the design of the S/H circuit becomes more challenging, and various solutions have been proposed to improve the speed of such S/H circuits. One prior art circuit solution for improving the speed of a S/H circuit is illustrated in prior art FIG. 3 and designated at reference numeral 30. The S/H circuit 30 consists of four S/H subcircuits 32a-32d coupled together in parallel. Each of the S/H subcircuits 32a-32d operates individually as a S/H circuit, wherein the input VIN is passed to the output VOUT during a xe2x80x9csampling modexe2x80x9d and the state of the input is maintained on the output in the xe2x80x9chold modexe2x80x9d, respectively.
The speed of the S/H circuit 30 of FIG. 3 is increased by using several individual S/H subcircuits interleaved in time. An exemplary sample timing diagram for the S/H circuit 30 is illustrated in prior art FIG. 4. Note that with multiple S/H subcircuits interleaved in time, each subcircuit transitions through one sample and hold cycle in four clock (CLK) cycles, whereas if a similar speed were desired with only a single S/H subcircuit, the sample and hold functions each would have to be completed within a one-half (1/2) clock cycle. Therefore in the above parallel configuration, the overall speed is increased without requiring higher performance from the individual S/H subcircuit elements.
Referring again to prior art FIG. 3, although the pass gates at the output of the overall S/H circuit 30 might seem like a possible speed limitation, usually such S/H circuits are followed by one or more output buffers. In such a case, the RC filter of the pass gate and the input capacitance of the output buffer is usually fairly small compared with the speed gained through parallelism.
One problem with the technique provided by the circuit 30 of prior art FIG. 3 is that if the S/H subcircuits 32a-32d are not perfectly matched, then errors can occur. The three chief types of mismatch associated with the S/H circuit 30 are offset mismatch, gain mismatch and timing mismatch. A brief discussion of the operation of an individual conventional S/H subcircuit is provided below in order to appreciate the impact that timing mismatch has on the performance of the S/H circuits 30.
An exemplary prior art sample and hold subcircuit is illustrated in prior art FIG. 5, and designated at reference numeral 40. Circuit 40 is a detailed circuit of structure 32a in FIG. 3. Transistor M1 operates as a sampling switch, and CHOLD acts as a sampling capacitor. In the sampling mode, a sampling signal xe2x80x9cSxe2x80x9d is asserted, thereby closing a switch 42, which activates M1 (turns M1 on). With M1 on, VIN is passed to the output VOUT.
A significant time point relating to timing mismatch in S/H circuits deals with the instant when the sampling switch M1 is deactivated, or turned off. Any deviation of the deactivation of M1 from perfect CLK/N time periods will cause a timing mismatch between the various subcircuits and result in distortion at the output VOUT. To deactivate M1, the sample signal xe2x80x9cASxe2x80x9d goes low and a hold signal xe2x80x9cHxe2x80x9d is asserted, which causes a switch 43 to close. This instance pulls the gate of M1 down to ground, thus turning M1 off. Each S/H subcircuit has its own hold signal xe2x80x9cHxe2x80x9d; consequently, a primary source of the timing mismatch relates to mismatches in the switch M1 driven by xe2x80x9cHxe2x80x9d and the arrival of the hold signal xe2x80x9cHxe2x80x9d at each subcircuit switch, respectively. In addition, even if no timing mismatch occurs between xe2x80x9cHxe2x80x9d signals of various subcircuits 32a-32d, a sizing mismatch of switch 43 or M1 between various subcircuits may exist which may contribute disadvantageously to timing mismatch.
There is a need in the art for a circuit and method for increasing the speed in sample and hold circuits in which timing mismatch is reduced substantially.
According to the present invention, a system and method of reducing timing mismatch in high speed S/H circuits is disclosed.
According to the present invention, timing mismatch related to the sampling switch in various S/H subcircuits is reduced by calibrating the subcircuits so that the hold signal of the subcircuits are synchronized with respect to the CLK signal, for example, by xe2x80x9ccatchingxe2x80x9d the CLK signal at the analog input for each subcircuit on its edge using the hold signal. In the above manner, a predetermined timing relationship between the clock signal and the hold signal is established for each S/H subcircuit. In the above manner, the timing mismatch between the various S/H subcircuits associated with the arrival of the hold signal at its switch in each subcircuit is reduced substantially or eliminated altogether.
According to one aspect of the present invention, subcircuits within a parallel S/H circuit are calibrated so as to reduce timing mismatch by feeding the CLK into the analog input of a S/H subcircuit input and analyzing the subcircuit output. Calibration occurs by modifying the hold signal such that a predetermined timing relationship is established between the CLK signal and the hold signal for each subcircuit, respectively.
According to another aspect of the present invention, a high speed S/H circuit comprises a plurality of S/H subcircuits coupled together in parallel and a calibration circuit associated therewith. The calibration circuit is operable to establish a predetermined timing relationship between a hold signal and the CLK signal for each of the S/H subcircuits. In an exemplary illustration of the present invention, the calibration circuit is selectively employable, and operates to feed the clock signal into each S/H subcircuit input and analyze each S/H subcircuit output with respect to the timing relationship between the hold signal and the CLK signal. Based on the various S/H subcircuit outputs, the hold (xe2x80x9cHxe2x80x9d) signal for each S/H subcircuit is modified, for example, delayed, in order to establish the desired timing relationship.
According to still another aspect of the present invention, a method for reducing timing mismatch in a S/H circuit is provided. The method comprises synchronizing a hold signal to a CLK signal by modifying the hold signal for each of a plurality of S/H subcircuits. The modified hold signals are then employed within the respective S/H subcircuits to thereby reduce the timing mismatch therebetween, thus reducing output distortion. In an exemplary illustration of the present invention, the synchronization of the CLK signal and the hold signal with a S/H subcircuit comprises inputting the CLK signal into an input of the S/H subcircuit. The S/H output is then used to determine a status of the CLK signal with respect to the hold signal. The status is then used to modify the hold signal for the subcircuits independently of one another, thereby altering a timing relationship between the CLK signal and the hold signal for the respective S/H subcircuits.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such embodiments and their equivalents. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.